VLSI ARENAVLSI Edu ↗Practice · Prove · Progress
Learn by
solving.
STA부터 architecture, DV, physical design와 analog까지 직접 풀고 설명하며 증명하는 반도체 엔지니어링 아레나입니다.
10 tracks.
One evidence ladder.
정답뿐 아니라 풀이, 재시도, 난이도와 공개 프로젝트 증거를 포트폴리오에 연결합니다.
Calculate the setup margin
A single-cycle path has the values below. Ignore jitter and uncertainty. What setup slack remains?
STAEasy02Place the responsibility
Which UVM component normally converts sequence items into pin-level DUT activity?
DVEasy03Diagnose a congested channel
Two large macros leave a narrow channel carrying many crossing nets. Which first action best tests the root cause?
Physical DesignMedium04Find the first-order pole
A 10 kΩ resistor and 2 pF capacitor form a first-order low-pass. What is the approximate pole frequency?
AnalogEasy05Order the UCIe releases
Which ordering is consistent with the consortium's listed releases?
ArchitectureEasy06Identify the CXL protocol name
Which listed name is one of the public CXL 3.0 protocol labels?
ArchitectureEasy07Calculate an ideal unit interval
Ignoring signaling details, what is the ideal UI for a 20 Gb/s line rate?
InterfaceEasy08Calculate payload efficiency
A transaction has 128 B payload and 32 B declared overhead. What is payload efficiency?
InterfaceEasy09Calculate raw memory capacity
A memory has 1024 addressable 32-bit words. What raw capacity results?
MemoryEasy10Calculate ideal pipeline latency
A four-stage pipeline has a 0.5 ns clock period and no stalls. What ideal latency is implied?
DigitalEasy11Evaluate simplified hold slack
Using the displayed convention, what hold slack results?
STAMedium12Calculate a simple cycle budget
What remaining budget follows from the stated model?
STAEasy13Calculate ideal dynamic power
With α=0.25, C=2 pF, V=1 V and f=100 MHz, what ideal switching power is estimated?
PowerMedium14Calculate steady-state temperature rise
For 2 W and θJA = 15 °C/W, what first-order temperature rise is estimated?
PackagingEasy15Calculate ideal ADC LSB
An ideal 10-bit converter spans 1 V. What ideal LSB results?
AnalogEasy16Calculate a simple wire resistance
For ρ=2e−8 Ω·m, L=100 µm and A=1 µm², what resistance is estimated?
Physical DesignMedium17Split current across ideal parallel vias
Under the equal-sharing assumption, 24 mA through 6 identical vias gives what current per via?
Physical DesignEasy18Identify the UVM driver role
Which UVM component conventionally translates sequence items into interface-level activity?
DVEasy19Choose the reproducibility record
Which extra detail is most necessary to make an open-PDK implementation result reproducible?
Physical DesignEasy20Identify an OpenROAD-safe claim
Which statement stays within documented OpenROAD project scope?
Physical DesignEasy